Design of a router for 3D single-chip network architectures

Global interconnects currently pose a challenge in the design of high-performance multiprocessor system-on-chip (MPSoC) systems. Researchers in the field of embedded systems are seeking solutions for on-chip communication architectures that offer low hardware costs, high reliability and predictability. One promising solution involves the use of interconnect networks based on the exchange of data packets, also known as Networks-on-Chip (NoCs). This could ultimately provide design and performance solutions to address the complexity of large-scale system-on-chip designs. It is within this context that our work is situated. Specifically, the aim is to model, design and validate a QoS router for a predefined 3D NoC architecture. Two models of this router have been developed: one in the VHDL language at the RTL (Register Transfer Level) and the other in the SystemC language at the TLM-T (Transaction Level Modelling with Time) level. The router architecture is validated in a 3D-Mesh topological network-on-a-chip.